After an IC device is manufactured, and prior to its release, the device is typically tested. During testing, the device under test (DUT) has its power provided by a power supply and shunt decoupling. However, for a DUT to be properly tested, a stable voltage must be provided while testing.
The problem of providing a stable voltage becomes increasingly challenging with high transistor count and higher frequency DUTs. Conventional Sort Interface Unit (SIU) and Test Interface Unit (TIU) designs utilize a bank of power supplies accompanied by (decoupling) capacitors. Nonetheless the power supplies are located some electrical distance away on a tester. This distance coupled with the electrical parasitics of the SIU/TIU limit its response time to changes in power demand of the DUT. This lack of response time allows the power (which in turn is directly related to voltage) to sag or droop for a finite time period.
As devices increase in frequency, they demand more power in the form of more current. This increased current draw also happens over a short time. The higher current demand over shorter time periods will cause a voltage droop proportional to the impedance. With other test conditions fixed, the higher the test frequency, the larger the voltage droop due to higher currents and shorter time periods. For any specific product, there is a maximum voltage droop that can be tolerated under normal device operation. Voltage droop is a limiting factor for the power delivery capability of SIU/TIU.